Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Computer-aided design tools generate the configuration data for programming the PLD from a description of a logic design. A designer uses a design capture tool to describe the logic components of the logic design and the connections between these logic components. This results in a textual description of the logic design in a hardware description language (HDL). A synthesis tool compiles the HDL description into a specification of the logic design using basic circuit elements, such as logic gates, look-up tables, and memory blocks. A placement tool places the circuit elements in the programmable logic of the PLD. A routing tool connects the placed circuit elements with nets routed through the programmable interconnect of the PLD. A programming tool generates the configuration data from the placed and routed logic design.
Analysis tools analyze the operating characteristics of the implementation of the logic design in the PLD. For example, timing analysis tools establish an operating frequency of the logic design implemented in the PLD. The operating characteristics of the implementation of the logic design in the PLD depend on the capabilities of these computer-aided design tools.
The present invention addresses one or more issues arising from the design flow described above.